The development of semiconductor switching technology for high power applications in motor drive circuits, appliance controls and lighting ballasts, for example, began with the bipolar junction transistor. As the technology matured, bipolar devices became capable of handling large current densities in the range of 40-50 A/cm.sup.2, with blocking voltages of 600 V.
Despite the attractive power ratings achieved by bipolar transistors, there exist several fundamental drawbacks to the suitability of bipolar transistors for all high power applications. First of all, bipolar transistors are current controlled devices. For example, a large control current into the base, typically one fifth to one tenth of the collector current, is required to maintain the device in an operating mode. Even larger base currents, however, are required for high speed forced turn-off. These characteristics make the base drive circuitry complex and expensive. The bipolar transistor is also vulnerable to breakdown if a high current and high voltage are simultaneously applied to the device, as commonly required in inductive power circuit applications, for example. Furthermore, it is difficult to parallel connect these devices since current diversion to a single device occurs at high temperatures, making emitter ballasting schemes necessary.
The power MOSFET was developed to address this base drive problem. In a power MOSFET, a gate electrode bias is applied for turn-on and turn-off control. Turn-on occurs when a conductive channel is formed between the MOSFET's source and drain regions under appropriate bias. The gate electrode is separated from the device's active area by an intervening insulator, typically silicon dioxide. Because the gate is insulated from the active area, little if any gate current is required in either the on-state or off-state. The gate current is also kept small during switching because the gate forms a capacitor with the device's active area. Thus, only charging and discharging current ("displacement current") is required. The high input impedance of the gate, caused by the insulator, is a primary feature of the power MOSFET. Moreover, because of the minimal current demands on the gate, the gate drive circuitry and devices can be easily implemented on a single chip. As compared to bipolar technology, the simple gate control provides for a large reduction in cost and a significant improvement in reliability.
These benefits are offset, however, by the high on-resistance of the MOSFET's active region, which arises from the absence of minority carrier injection. As a result, the device's operating forward current density is limited to relatively low values, typically in the range of 10 A/cm.sup.2, for a 600 V device, as compared to 40-50 A/cm.sup.2 for the bipolar transistor.
On the basis of these features of power bipolar transistors and MOSFET devices, hybrid devices embodying a combination of bipolar current conduction with MOS-controlled current flow were developed and found to provide significant advantages over single technologies such as bipolar or MOSFET alone. Classes of such hybrid devices include various types of MOS-gated thyristors as well as the insulated gate bipolar transistor (IGBT), also commonly referred to by the acronyms COMFET (Conductivity-Modulated FET) and BIFET (Bipolar-mode MOSFET). Related hybrid devices are also disclosed in U.S. Pat. No. 5,396,087 to Baliga entitled Insulated Gate Bipolar Transistor with Reduced Susceptibility to Parasitic Latch-Up, U.S. Pat. No. 5,488,236 to Baliga et al. entitled Latch-Up Resistant Bipolar Transistor with Trench IGFET and Buried Collector, and U.S. Pat. No. 5,034,336 to Seki entitled Method of Producing Insulated Gate Bipolar Transistor.
One example of an insulated-gate bipolar transistor (IGBT) is illustrated by FIG. 1. In particular, FIG. 1 illustrates a conventional IGBT comprising a vertical PNP bipolar transistor (BJT) and a lateral N-channel MOSFET for controlling turn-on and turn-off of the vertical BJT. As illustrated, a P+ emitter region 12 is provided as a substrate on which an N+ buffer region 13 is formed. A relatively thick and lightly doped N- drift region 14 is also provided on the buffer region, opposite the emitter region 12. A P-type base or collector region 19 is also provided in the drift region 14 and extends to an upper surface thereof. A least one source region 25 is also provided in the base/collector region 19 and an insulated gate electrode, comprising an insulating layer 15 and a gate electrode 16, is provided on the upper surface, opposite a peripheral edge of the base region 19. As will be understood by those skilled in the art, forward conduction in the illustrated IGBT is established by forward biasing the emitter region 12 relative to the base/collector region 19 and applying a turn-on gate bias to the gate electrode 16. Upon application of a sufficient gate bias, an inversion-layer channel is formed in the base region 19, at a portion of the upper surface of the base region 19 extending between the source region 25 and the drift region 14. This inversion-layer channel (not shown) initiates turn-on by providing base drive current in the form of electrons to the drift region 14 (which acts as the "base" of the vertical PNP transistor). The magnitude of the gate bias needed to establish the inversion-layer channel is a function of the doping concentration in the base region 19, at the upper surface between the source region 25 and drift region 14. The base region 19 also acts as a collector of holes supplied by the emitter region 12, during forward conduction. These collected holes are then swept to a collector contact 29 which is electrically insulated from the gate electrode 16 by a sidewall insulating layer 28. Turn-off of the vertical bipolar transistor can also be achieved by eliminating the inversion-layer channel in the base region 19 by removing the gate bias. However, as explained below, forward current conduction may not always be terminated by removal of the gate bias alone.
As will be understood by those skilled in the art, the base/collector region 19 may be formed by implanting P-type dopants into the upper surface of the drift region 14, using the insulated gate electrode as an implant mask and then diffusing the implanted P-type dopants. The at least one source region 25 may also be formed as an annular-shaped source region in a polygonal-shaped base region 19 (e.g., circular, square, hexagonal, etc.) or as a pair of parallel stripes in a stripe-shaped base region 19, for example. To inhibit the likelihood that the parasitic P-N-P-N thyristor formed by regions 12-14, 19 and 25 will latch-up under high forward current conduction conditions, a central P+ contact region 30 may also be provided to lower the effective lateral resistance in the base region 19 and thereby reduce the magnitude of the forward bias appearing across the base/source junction. Thus, during heavy forward conduction, the P-N junction formed between the base region 19 and the at least one source region 25 will be less susceptible to turn-on. Such turn-on is necessary in order for the parasitic thyristor to latch-up. As will be understood by those skilled in the art, the central P+ contact region 30 may be formed by implanting P-type dopants into the base region 19, using the sidewall insulating layer 28 as an implant mask.
Unfortunately, notwithstanding the above described attempt to limit the likelihood of parasitic thyristor latch-up by incorporating a relatively highly doped P+ central contact region 30, there still continues to be a need for power semiconductor devices such as IGBTs which have reduced susceptibility to latch-up.